1. Field of the Invention
The present invention relates to line interface devices, and, in particular, to a CMOS transmission line driver that is used for interfacing CMOS digital circuits to transmission lines.
2. Description of the Related Art
Digital systems typically include several Very Large Scale Integrated (VLSI) circuits that cooperate and communicate with one-another to perform a desired task. FIG. 1 illustrates a typical digital system. The VLSI circuits are mounted on several circuit boards that are referred to as "daughter boards". Each daughter board may accommodate several VLSI circuits. In turn, the daughter boards are received by a "mother board" that has circuitry for facilitating communication between the individual daughter boards.
The individual VLSI circuits are interconnected for binary communication by transmission mediums. The transmission mediums are generally collected together to form buses. The number, size and types of buses that are used in a digital system may be designed for general-purpose applications or according to a more specific, industry standard data-communications configuration. One such industry standard is the so-called IEEE 896.1 Futurebus+ standard. The Futurebus+ standard provides a protocol for implementing an internal computer bus architecture.
FIG. 1 illustrates the hierarchy of the several different bus levels utilizable in a Futurebus+ system. A "component level bus" is used to interconnect the several VLSI circuits that are located on a single daughter board, and a "backplane bus" is used to interconnect the VLSI circuits of one daughter board to the VLSI circuits of another daughter board. Thus, a component level bus is constructed on each daughter board, and a backplane bus is constructed on the mother board.
The transmission mediums which form the component and backplane buses are typically traces which are formed on the printed circuit board (PCB) substrates of the daughter and mother boards. Microstrip traces and strip line traces can be employed to form transmission lines having characteristic impedances on the order of about 50.OMEGA.-70.OMEGA.. Such transmission lines usually have their opposite ends terminated in their characteristic impedance. Because of the parallel resistive terminations, the effective resistance of the transmission line may be as low as 25.OMEGA.-35.OMEGA..
Data transceivers (TRANSmitter/reCEIVER) are used to interface the VLSI circuits to the transmission medium. FIG. 2 illustrates the positioning of a data transceiver between the backplane bus of a Futurebus+ system and the data bus of a VLSI circuit to facilitate communications between the VLSI circuit and the rest of the digital system.
A data transceiver is a read/write terminal capable of transmitting information to and receiving information from the transmission medium. A transceiver typically includes a line driver stage (or simply "driver") and a receiver stage (or simply "receiver"). The common purpose of transmission line drivers and receivers is to transmit data quickly and reliably through a variety of environments over electrically long distances. This task is complicated by the fact that externally introduced noise and ground shifts can severely degrade the data.
Drivers amplify digital signal outputs from the VLSI circuitry so that the signals can be properly transmitted on the transmission medium. Receivers are typically differential amplifiers that receive signals from the transmission medium and provide outputs to the VLSI circuitry that are representative of digital information received from the medium.
Conventional drivers usually include level shifting capability to provide compatibility with different integrated circuit technologies. Specifically, before a driver transmits a signal across a transmission medium, the driver changes the nominal voltage swing (or the "dynamic signal range") utilized by the VLSI circuitry, e.g., CMOS, TTL, ECL, etc., to a different voltage swing that is utilized by the transmission medium. Thus, a driver not only amplifies a digital signal, but it changes the nominal voltage swing of the signal as well.
CMOS technology is attractive for implementing VLSI circuits with high density and with much lower power dissipation than its bipolar counterpart. However, standard TTL or CMOS circuits operate between 5 Volts and ground which causes them to dissipate excessive amounts of power when driving terminated transmission lines. ECL has been used for many years to drive terminated transmission lines; however, ECL has relatively high power dissipation.
A different nominal voltage swing is normally used when transmitting data across a transmission medium in order to conserve power. Specifically, the power internally dissipated by the driver is proportional to the nominal voltage swing of the binary signal it applies to the transmission line. Therefore, power dissipation is reduced if the driver transmits a signal having a relatively small voltage swing over the transmission line.
It has become common for signals to be transmitted over transmission lines at BTL (Backplane Transceiver Logic) signal levels. The signal level standard is denoted "Backplane" because BTL has been used primarily in the backplane buses of mother boards. Because the nominal voltage swing of BTL is 1.0 Volt (logic low) to 2.1 Volts (logic high), power dissipation is less than it would be if the signals were transmitted over the transmission lines at CMOS (0 Volts to 3.3 Volts, or, 0 Volts to 5 Volts) or TTL (0 volts to 3.5 Volts) signal levels.
Signals have also been transmitted over transmission lines at the so-called "GTL" signal levels disclosed in U.S. Pat. No. 5,023,488 to Gunning ("Gunning"). Gunning discloses such GTL drivers and receivers for interfacing VLSI CMOS circuits to transmission lines. The nominal voltage swing of GTL is 0.3 Volts (logic low) to 1.2 Volts (logic high).
FIG. 3 shows the basic GTL driver 10 that is disclosed in Gunning. A very wide channel, open drain, N-channel CMOS transistor M1 is used for transforming binary signals to a transmission line 12 from a more or less conventional CMOS signal source 14 which effectively isolates the transmission line 12 from the ordinary 5 v rail-to-rail signal swing of the signal source 14. Transistor M1 has its gate connected to the output of the signal source 14, its drain connected to the transmission line 12, and its source returned to ground (i.e., the same reference level as the 0 v rail of the signal source 14).
The rate at which the transistor M1 responds to transitions in the binary signal supplied by the signal source 14 is dependent upon the rate at which transistor M1's gate capacitance charges and discharges. Therefore, for higher frequency operations, the output stage of the signal source 14 is an inverter comprising a p-channel transistor M2 and an n-channel transistor M3. Transistors M2 and M3 are connected in a standard inverter configuration. More particularly, they have their gates connected to a signal node V.sub.IN within the signal source 14, their drains connected to the gate of the transistor M1, and their sources connected to the 5 v rail and the 0 v rail, respectively, of signal source 14.
In operation, when the signal at V.sub.IN drops to a low ("0") logic level, transistors M2 and M3 are switched into and out of conduction, respectively. Thus, the gate capacitance of transistor M1 is charged relatively rapidly by the current conducted by the source-drain circuit of transistor M2. The gate of transistor M1 is quickly pulled up toward the 5 Volt rail of the signal source 14, thereby causing transistor M1 to promptly switch into conduction. On the other hand, when the signal V.sub.IN increases to a high ("1") logic level, transistor M2 switches out of conduction while transistor M3 switches into conduction. This causes the gate capacitance of transistor M1 to be quickly discharged by the current conducted by the source-drain circuit of transistor M3 so that the gate of transistor M1 is pulled down relatively rapidly toward the 0 Volt rail of the signal source 14, thereby promptly switching transistor M1 out of conduction.
The signal level on the transmission line 12 tends to stabilize substantially at the voltage level to which the transmission line 12 is terminated a short time after transistor M1 is switched out of conduction (i.e., as soon as the switching transients have settled out). On the other hand, when transistor M1 is switched into conduction, its source-drain circuit provides a ground return path for current flow through the terminating resistors 16 and 18. The signal level at which the transmission line 12 tends to stabilize (again, after the switching transients have settled out) is determined by the voltage division which the parallel terminating resistor 16 and 18 and the source-drain resistance of the conductive transistor M1 perform on the voltage to which the transmission line 12 is terminated.
The effective voltage dividing ratio of the divider is determined to a first approximation by the ratio of the source-drain resistance of transistor M1 in its conductive state to the sum of that resistance plus the effective resistance of the parallel terminating resistors 16 and 18. Thus, for example, if the low ("0") signal level on the transmission line 12 is selected to be approximately 0.3 Volts to provide a signal swing of approximately 1.0 Volts, the channel width of the transistor M1 ordinarily has to be orders of magnitude greater than its channel length to reduce the effective resistance of its source-drain circuit in conduction to a suitably low level. The optimal channel width-to-channel length ratio of transistor M1 depends on several process and application specific variables, but a ratio of about 1000:1 is typical at the current state of the art.
FIG. 4 shows a GTL driver 20 with a damping circuit. Specifically, provision is made in the driver 20 for damping certain of the switching transients which are generated when transistor M1 is switched into and out of conduction. These improvements permit the GTL signal swing to be reduced to a swing of about 0.8 Volts between an upper limit of approximately 1.2 Volts and a lower limit of about 0.4 Volts.
Some of the more troublesome switching transients occur when transistor M1 is switched from a conductive state to a non-conductive state. The drain-side parasitic packaging inductance and the drain-side parasitic capacitances of transistor M1 form a ringing circuit which tends to cause the voltage on the transmission line 12 to overshoot its nominal upper limit by a substantial margin and to oscillate for a prolonged period of time. Similarly, the source-side parasitic inductances and capacitances of transistor M1 form another ringing circuit which tends to cause a potentially troublesome oscillatory "ground bounce" perturbance of the reference voltage on the low level rail of the CMOS circuit.
To reduce these switching transients, the driver 20 is equipped with a feedback circuit for briefly connecting the drain of transistor M1 to its gate when transistor M1 is switched from a conductive state to a non-conductive state. The feedback circuit includes a pair of n-channel transistors M4 and M5 which have their source-drain circuits connected in series between the drain and gate of transistor M1. The input V.sub.IN for the driver 20 is coupled to the gate of transistor M5, and two additional inverter stages 22 and 24 are coupled between the inverter 14 and the gate of transistor M4.
During operation, a low ("0") logic level signal at V.sub.IN holds transistor M5 in a non-conductive state and transistors M1 and M4 in conductive states. However, shortly after the logic level of the signal at V.sub.IN increases to a high ("1") logic level, the p-channel transistor M2 and the n-channel transistor M3 of the asymmetric inverter stage 14 switch out of and into conduction, respectively. Transistor M3 tends to pull the gate of transistor M1 down toward ground, but transistor M5 is now switched into conduction, so it completes a feedback path between the drain and the gate of transistor M1. Transistor M3 is relatively weak (i.e., it has a significantly higher source-drain resistance than the other transistors), so most of the discharge current for the gate capacitance of transistor M1 is drawn through the drain-source circuit of transistor M1 via transistors M4 and M5.
As the gate voltage of transistor M1 drops, its drain voltage increase. However, the feedback path provided by the transistors M4 and M5 precludes the drain voltage of transistor M1 from increasing to a level significantly above its gate voltage. This limits the rate at which the current flowing through the parasitic inductances changes, thereby limiting the rates at which the drain-side capacitances, the source-side capacitances, and the gate-substrate capacitance discharge. Accordingly, the drain-side voltage overshoot and the source-side ground bounce are damped. Finally, about one nanosecond after transistor M5 is switched into conduction, the output of the last inverter stage 24 drops to a low ("0") logic level, so the feedback loop then is re-opened to permit the transistor M1 to switch completely out of conduction.
The GTL driver 20 disclosed in Gunning suffers from a number of disadvantages. First, the feedback circuit that is used to control the rising edge of V.sub.OUT prevents the drain voltage of transistor M1 from increasing to a level significantly above its gate voltage. Because the drain voltage is held low, V.sub.OUT cannot go high until the feedback circuit is disabled which increases the propagation delay of the driver 20.
A second disadvantage of the driver 20 is that its rise time t.sub.r, fall time t.sub.f, edge rate, turn-on delay, turn-off delay, and propagation delay are sensitive to temperature variations, supply voltage variations, and process variations.
A third disadvantage of the driver 20 is that its minimum rise time t.sub.r and fall time t.sub.f are too fast which causes ground bouncing, output over-shooting, and large cross-talk.
These disadvantages cause output pulse distortion.
Thus, there is a need for a transmission line driver that provides an output voltage swing of approximately 0.3 Volts (logic low) to 1.2 Volts (logic high) and that overcomes the disadvantages of the GTL drivers discussed above.